AT292859T

Phase-locked loop based clock phasing implementing a virtual delay

Abstract

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Term

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13 members in 7 offices

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0001029SwedenA
0100174SwedenW

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SE0001029D0SwedenD0
SE0001029LSwedenL
WO0171920A1World Intellectual Property Organization (WIPO)A1
AU3251501AAustraliaA
US2001030559A1United States of AmericaA1
US6366146B2United States of AmericaB2
SE517967C2SwedenC2
EP1277285A1European Patent Office (EPO)A1
EP1277285B1European Patent Office (EPO)B1
AT292859TThis recordAustriaT
ATE292859T1AustriaT1
DE60109912D1GermanyD1
DE60109912T2GermanyT2