Test pattern compression for an integrated circuit test environment

(57) How to compress the test pattern applied to the scanning chain in a circuit during a summary test. It has that this method generates the notation in relation to the scanning cell in a scanning chain. A notation is created by assigning a variable to the bit on the input channel of the exterior supplied to the circuit during the test. Symbolic simulation is used, and a variable is applied to a deconstructivism presser, in order to obtain a notation. In order that a test cube may test the obstacle in an integrated circuit, by making the assigned value in a test cube equal to the notation relevant to a corresponding scanning cell, an one-set equation is formal and is expressed. It is created using the deterministic pattern which assigns a value to a scanning cell. An equation is solved in order to obtain the compressed test pattern.