AT284075T - Semiconductor processing method comprising the fabrication of a barrier layer

20 members in 8 offices

This recordMember, by publication datePriority claim

Priority claims
Document	Office	Kind	Date
99405497	United States of America	A	1997-12-19
9827106	United States of America	W	1998-12-18

Family members, oldest first
Document	Office	Kind
WO9933098A1	World Intellectual Property Organization (WIPO)	A1	1999-07-01
AU2005999A	Australia	A	1999-07-12
EP1042802A1	European Patent Office (EPO)	A1	2000-10-11
US6165833A	United States of America	A	2000-12-26
KR20010033186A	Republic of Korea	A	2001-04-25
US2002004279A1	United States of America	A1	2002-01-10
JP2002512435A	Japan	A	2002-04-23
US2003030093A1	United States of America	A1	2003-02-13
US6593183B1	United States of America	B1	2003-07-15
KR100455799B1	Republic of Korea	B1	2004-11-08
EP1042802B1	European Patent Office (EPO)	B1	2004-12-01
AT284075TThis record	Austria	T	2004-12-15
ATE284075T1	Austria	T1	2004-12-15
DE69827974D1	Germany	D1	2005-01-05
EP1508914A2	European Patent Office (EPO)	A2	2005-02-23
EP1508914A3	European Patent Office (EPO)	A3	2005-05-25
JP3663128B2	Japan	B2	2005-06-22
US6911371B2	United States of America	B2	2005-06-28
DE69827974T2	Germany	T2	2005-11-24
US7205600B2	United States of America	B2	2007-04-17

1 legal event, as the office reported them to INPADOC

Legal events, newest first
	Event	Code
2005-06-15	Ceased as to paragraph 5 lit. 3 law introducing patent treatiesCeasedRER	RER

German: HALBLEITER VERARBEITUNGVERFAHREN MIT DER HERSTELLUNG VON EINER SPERRSCHICHT
English: SEMICONDUCTOR PROCESSING WITH THE PRODUCTION OF A SHOCK LAYER

CPC, 14: H01L28/40
H01L21/3205
H01L21/76829
H01L21/76834
H01L21/76838
H01L23/5222
H01L27/10855
H01L27/10894
H01L28/57
H01L28/84
H01L28/91
H10B12/0335
H01L2924/0002
H10B12/09
Filled: the office’s first classification
IPC, 6: H01L21 283
H01L21 02
H01L21 768
H01L21 8242
H01L23 522
H01L27 108

Semiconductor processing method comprising the fabrication of a barrier layer