Controlling threading dislocation densities using graded layers and planarization

(57) Semiconductor structure equipped with the 1st layer with the surface which is at least one 1st crystallinity epitaxial layer (304) on a summary semiconductor board (302) and this substrate, and was made flat, and at least one 2nd crystallinity epitaxial layer (306) on that 1st layer. In the another embodiment of the present invention, a semiconductor structure equipped with a semiconductor board and the GeSi (306, 308) inclination domain grown-up on the substrate is offered, and compressive strain which were incorporated at the time of heat treatment and which pull and offset distortion are included in the inclination domain. The 1st layer that has the inclination domain (304) grown-up on a semiconductor board and this substrate in the another embodiment of the present invention, Preparation る半導体 structure is offered, it pulls, compressive strain are incorporated that distortion should be offset, the 1st above-mentioned layer has the field which is included in the above-mentioned inclination domain between heat treatment and which was made flat, and the 2nd layer (306, 308) is prepared on the 1st above-mentioned layer.