Sdram controller for parallel processor architecture

Compromised a parallel, method for a multithreaded processor. The processor and matched with the system functions the general processor and supporting multi-hardware of multiple micro master. The processor further - comprising a storage 1st control unit and 2nd memory controlling data memory (control system, the front storage control unit is alignment the even number memory connected with the movable on the odd number memory connecting device of the classification to the memory indicator according to the memory pointer, the rear memory is a pointer according to the memory type or writing the pointer is arranged on the optimization to the memory test.