Memory device command signal generator

(57) The command generation machine for a summary dynamic random access memory decreases a counter from the initial counter value which is a function of a clock rate. The output of a counter is decoded and generates various command signals for DRAM. Especially each command signal is generated by each counter value, and correspondence with a counter value and a command signal is a function of a clock rate. Counters decrease in number from a larger initial value in a larger clock rate, and a command signal is published by the decoder with a larger counter value than the case of a generally more large clock rate. As a result of there being no correspondence between the clock cycle number which happens between Memory Access, and the timing of a command signal, the timing of a command signal may be chosen in spite of a substantial change of a clock rate so that the speed of DRAM desired may be optimized.