Microprocessor cache consistency

(57) The method of the memory control in the microprocessor system which consists of summary 2 or a processor beyond it (40, 42) is shown. Each processor (40, 42) has cache memory (44, 46), this system has a system memory (48), a system memory (48) is divided into a page, and the page is further subdivided by the block. This method is related with management of the system memory (48) by identifying the domain of a system memory (48) as "possible cash ", "noncacheable", and "opening. "The safety feature for ensuring for the block of a system memory (48) not to be simultaneously cached by two different processors (40, 42) is supplied.