AT128254T
Digital clock buffer circuit providing controllable delay
Abstract
This record has no abstract on file.
Term
No projected expiry on record.
- Priority
- Filed
- Granted
- Today
14 members in 8 offices
Priority claims1
| Document | Office | Kind | Date |
|---|---|---|---|
| 48907990 | United States of America | A |
Members14
| Document | Office | Kind | |
|---|---|---|---|
| AU7106191A | Australia | A | |
| CA2037593A1 | Canada | A1 | |
| EP0445574A2 | European Patent Office (EPO) | A2 | |
| IE910706A1 | Ireland | A1 | |
| US5118975A | United States of America | A | |
| JPH04219022A | Japan | A | |
| EP0445574A3 | European Patent Office (EPO) | A3 | |
| US5212484A | United States of America | A | |
| AU640448B2 | Australia | B2 | |
| EP0445574B1 | European Patent Office (EPO) | B1 | |
| AT128254TThis record | Austria | T | |
| DE69113083D1 | Germany | D1 | |
| DE69113083T2 | Germany | T2 | |
| JP2892515B2 | Japan | B2 |
1 legal event, as the office reported them to INPADOC
Events
| Event | Code | |
|---|---|---|
| Ceased as to paragraph 5 lit. 3 law introducing patent treatiesCeasedRER | RER |
Numbers
- Application
- 91102364
Titles2
- German
- DIGITALE TAKTPUFFERSCHALTUNG MIT REGELBARER VERZÖGERUNG.
- English
- DIGITAL TAKE-UP CONTROL WITH REGULAR DELAY.
Classification
- CPC, 5
- G06F1/10
- H03L7/0814
- H03L7/087
- H03L7/0816
- H03L7/089
- IPC, 7
- H03K5 135
- G06F1 10
- G11C11 407
- H03L7 00
- H03L7 081
- H03L7 087
- H03L7 089